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PART ONE SOLID STATE ELECTRONIC AND DEVICES1

CHAPTER 1 INTRODUCTION TO ELECTRONICS3

1.1 A Brief History of Electronics：From Vacuum Tubes to Giga-Scale Integration5

1.2 Classifiication of Electronic Signals8

1.2.1 Digital Signals9

1.2.2 Analog Signals9

1.2.3 A/D and D/A Converters—Bridging the Analog and Digital Domains10

1.3 Notational Conventions12

1.4 Problem-Solving Approach13

1.5 Important Concepts from Circuit Theory15

1.5.1 Voltage and Current Division15

1.5.2 Thevenin and Norton Circuit Representations16

1.6 Frequency Spectrum of Electronic Signals21

1.7 Amplifiers22

1.7.1 Ideal Operational Amplifiers23

1.7.2 Amplifier Frequency Response25

1.8 Element Variations in Circuit Design26

1.8.1 Mathematical Modeling of Tolerances26

1.8.2 Worst-Case Analysis27

1.8.3 Monte Carlo Analysis29

1.8.4 Temperature Coeffiicients32

1.9 Numeric Precision34

Summary34

Key Terms35

References36

Additional Reading36

Problems37

CHAPTER 2 SOLID-STATE ELECTRONICS42

2.1 Solid-State Electronic Materials44

2.2 Covalent Bond Model45

2.3 Drift Currents and Mobility in Semiconductors48

2.3.1 Drift Currents48

2.3.2 Mobility49

2.3.3 Velocity Saturation49

2.4 Resistivity of Intrinsic Silicon50

2.5 Impurities in Semiconductors51

2.5.1 Donor Impurities in Silicon52

2.5.2 Acceptor Impurities in Silicon52

2.6 Electron and Hole Concentrations in Doped Semiconductors52

2.6.1 n-Type Material （ND ＞ NA）53

2.6.2 p-Type Material （NA ＞ND）54

2.7 Mobility and Resistivity in Doped Semiconductors55

2.8 Diffusion Currents59

2.9 Total Current60

2.10 Energy Band Model61

2.10.1 Electron-Hole Pair Generation in an Intrinsic Semiconductor61

2.10.2 Energy Band Model for a Doped Semiconductor62

2.10.3 Compensated Semiconductors62

2.11 Overview of Integrated Circuit Fabrication64

Summary67

Key Terms68

Reference69

Additional Reading69

Important Equations69

Problems70

CHAPTER 3 SOLID-STATE DIODES AND DIODE CIRCUITS74

3.1 The pn Junction Diode75

3.1.1 pn Junction Electrostatics75

3.1.2 Internal Diode Currents79

3.2 The i-v Characteristics of the Diode80

3.3 The Diode Equation：A Mathematical Model for the Diode82

3.4 Diode Characteristics Under Reverse，Zero，and Forward Bias85

3.4.1 Reverse Bias85

3.4.2 Zero Bias85

3.4.3 Forward Bias86

3.5 Diode Temperature Coefficient89

3.6 Diodes Under Reverse Bias89

3.6.1 Saturation Current in Real Diodes90

3.6.2 Reverse Breakdown91

3.6.3 Diode Model for the Breakdown Region92

3.7 pn Junction Capacitance92

3.7.1 Reverse Bias92

3.7.2 Forward Bias93

3.8 Schottky Barrier Diode93

3.9 Diode SPICE Model and Layout94

3.10 Diode Circuit Analysis96

3.10.1 Load-Line Analysis96

3.10.2 Analysis Using the Mathematical Model for the Diode98

3.10.3 The Ideal Diode Model102

3.10.4 Constant Voltage Drop Model104

3.10.5 Model Comparison and Discussion105

3.11 Multiple-Diode Circuits106

3.12 Analysis of Diodes Operating in the Breakdown Region109

3.12.1 Load-Line Analysis109

3.12.2 Analysis with the Piecewise Linear Model109

3.12.3 Voltage Regulation110

3.12.4 Analysis Including Zener Resistance111

3.12.5 Line and Load Regulation112

3.13 Half-Wave Rectifiier Circuits113

3.13.1 Half-Wave Rectifiier with Resistor Load113

3.13.2 Rectifier Filter Capacitor114

3.13.3 Half-Wave Rectifiier with RC Load115

3.13.4 Ripple Voltage and Conduction Interval116

3.13.5 Diode Current118

3.13.6 Surge Current120

3.13.7 Peak-Inverse-Voltage （PIV） Rating120

3.13.8 Diode Power Dissipation120

3.13.9 Half-Wave Rectifier with Negative Output Voltage121

3.14 Full-Wave Rectifiier Circuits123

3.14.1 Full-Wave Rectifier with Negative Output Voltage124

3.15 Full-Wave Bridge Rectification125

3.16 Rectifiier Comparison and Design Tradeoffs125

3.17 Dynamic Switching Behavior of the Diode129

3.18 Photo Diodes，Solar Cells，and Light-Emitting Diodes130

3.18.1 Photo Diodes and Photodetectors130

3.18.2 Power Generation from Solar Cells131

3.18.3 Light-Emitting Diodes （LEDs）132

Summary133

Key Terms134

Reference135

Additional Reading135

Problems135

CHAPTER 4 FIELD-EFFECT TRANSISTORS145

4.1 Characteristics of the MOS Capacitor146

4.1.1 Accumulation Region147

4.1.2 Depletion Region148

4.1.3 Inversion Region148

4.2 The NMOS Transistor148

4.2.1 Qualitative i-v Behavior of the NMOS Transistor149

4.2.2 Triode Region Characteristics of the NMOS Transistor150

4.2.3 On Resistance153

4.2.4 Saturation of the i-v Characteristics154

4.2.5 Mathematical Model in the Saturation （Pinch-Off） Region155

4.2.6 Transconductance157

4.2.7 Channel-Length Modulation157

4.2.8 Transfer Characteristics and Depletion-Mode MOSFETS158

4.2.9 Body Effect or Substrate Sensitivity159

4.3 PMOS Transistors161

4.4 MOSFET Circuit Symbols163

4.5 Capacitances in MOS Transistors165

4.5.1 NMOS Transistor Capacitances in the Triode Region165

4.5.2 Capacitances in the Saturation Region166

4.5.3 Capacitances in Cutoff166

4.6 MOSFET Modeling in SPICE167

4.7 MOS Transistor Scaling169

4.7.1 Drain Current169

4.7.2 Gate Capacitance169

4.7.3 Circuit and Power Densities170

4.7.4 Power-Delay Product170

4.7.5 Cutoff Frequency171

4.7.6 High Field Limitations171

4.7.7 Subthreshold Conduction172

4.8 MOS Transistor Fabrication and Layout Design Rules172

4.8.1 Minimum Feature Size and Alignment Tolerance173

4.8.2 MOS Transistor Layout173

4.9 Biasing the NMOS Field-Effect Transistor176

4.9.1 Why Do We Need Bias？176

4.9.2 Constant Gate-Source Voltage Bias178

4.9.3 Load Line Analysis for the Q-Point181

4.9.4 Four-Resistor Biasing182

4.10 Biasing the PMOS Field-Effect Transistor188

4.11 The Junction Field-Effect Transistor （IFET）190

4.11.1 The JFET with Bias Applied191

4.11.2 JFET Channel with Drain-Source Bias191

4.11.3 n-Channel JFET i-v Characteristics193

4.11.4 The p-Channel JFET195

4.11.5 Circuit Symbols and JFET Model Summary195

4.11.6 JFET Capacitances196

4.12 JFET Modeling in SPICE197

4.13 Biasing the JFET and Depletion-Mode MOSFET198

Summary200

Key Terms202

References203

Problems204

CHAPTER 5 BIPOLAR JUNCTION TRANSISTORS217

5.1 Physical Structure of the Bipolar Transistor218

5.2 The Transport Model for the npn Transistor219

5.2.1 Forward Characteristics220

5.2.2 Reverse Characteristics222

5.2.3 The Complete Transport Model Equations for Arbitrary Bias Conditions223

5.3 The pnp Transistor225

5.4 Equivalent Circuit Representations for the Transport Models227

5.5 The i-v Characteristics of the Bipolar Transistor228

5.5.1 Output Characteristics228

5.5.2 Transfer Characteristics229

5.6 The Operating Regions of the Bipolar Transistor230

5.7 Transport Model Simplifiications231

5.7.1 Simplified Model for the Cutoff Region231

5.7.2 Model Simplifications for the Forward-Active Region233

5.7.3 Diodes in Bipolar Integrated Circuits239

5.7.4 Simplifiied Model for the Reverse-Active Region240

5.7.5 Modeling Operation in the Saturation Region242

5.8 Nonideal Behavior of the Bipolar Transistor245

5.8.1 Junction Breakdown Voltages246

5.8.2 Minority-Carrier Transport in the Base Region246

5.8.3 Base Transit Time247

5.8.4 Diffusion Capacitance249

5.8.5 Frequency Dependence of the Common-Emitter Current Gain250

5.8.6 The Early Effect and Early Voltage250

5.8.7 Modeling the Early Effect251

5.8.8 Origin of the Early Effect251

5.9 Transconductance252

5.10 Bipolar Technology and SPICE Model253

5.10.1 Qualitative Description253

5.10.2 SPICE Model Equations254

5.10.3 High-Performance Bipolar Transistors255

5.11 Practical Bias Circuits for the BJT256

5.11.1 Four-Resistor Bias Network258

5.11.2 Design Objectives for the Four-Resistor Bias Network260

5.11.3 Iterative Analysis of the Four-Resistor Bias Circuit266

5.12 Tolerances in Bias Circuits266

5.12.1 Worst-Case Analysis267

5.12.2 Monte Carlo Analysis269

Summary272

Key Terms274

References274

Problems275

PART TWO DIGITAL ELECTRONICS285

CHAPTER 6 INTRODUCTION TO DIGITAL ELECTRONICS287

6.1 Ideal Logic Gates289

6.2 Logic Level Definitions and Noise Margins289

6.2.1 Logic Voltage Levels291

6.2.2 Noise Margins291

6.2.3 Logic Gate Design Goals292

6.3 Dynamic Response of Logic Gates293

6.3.1 Rise Time and Fall Time293

6.3.2 Propagation Delay294

6.3.3 Power-Delay Product294

6.4 Review of Boolean Algebra295

6.5 NMOS Logic Design297

6.5.1 NMOS Inverter with Resistive Load298

6.5.2 Design of the W/L Ratio of Ms299

6.5.3 Load Resistor Design300

6.5.4 Load-Line Visualization300

6.5.5 On-Resistance of the Switching Device302

6.5.6 Noise Margin Analysis303

6.5.7 Calculation of V IL and VOH303

6.5.8 Calculation of V I H and VOL304

6.5.9 Load Resistor Problems305

6.6 Transistor Alternatives to the Load Resistor306

6.6.1 The NMOS Saturated Load Inverter307

6.6.2 NMOS Inverter with a Linear Load Device315

6.6.3 NMOS Inverter with a Depletion-Mode Load316

6.6.4 Static Design of the Pseudo NMOS Inverter319

6.7 NMOS Inverter Summary and Comparison323

6.8 NMOS NAND and NOR Gates324

6.8.1 NOR Gates325

6.8.2 NAND Gates326

6.8.3 NOR and NAND Gate Layouts in NMOS Depletion-Mode Technology327

6.9 Complex NMOS Logic Design328

6.10 Power Dissipation333

6.10.1 Static Power Dissipation333

6.10.2 Dynamic Power Dissipation334

6.10.3 Power Scaling in MOS Logic Gates335

6.11 Dynamic Behavior of MOS Logic Gates337

6.11.1 Capacitances in Logic Circuits337

6.11.2 Dynamic Response of the NMOS Inverter with a Resistive Load338

6.11.3 Pseudo NMOS Inverter343

6.11.4 A Final Comparison of NMOS Inverter Delays344

6.11.5 Scaling Based Upon Reference Circuit Simulation346

6.11.6 Ring Oscillator Measurement of Intrinsic Gate Delay346

6.11.7 Unloaded Inverter Delay347

6.12 PMOS Logic349

6.12.1 PMOS Inverters349

6.12.2 NOR and NAND Gates352

Summary352

Key Terms354

References355

Additional Reading355

Problems355

CHAPTER 7 COMPLEMENTARY MOS （CMOS） LOGIC DESIGN367

7.1 CMOS Inverter Technology368

7.1.1 CMOS Inverter Layout370

7.2 Static Characteristics of the CMOS Inverter370

7.2.1 CMOS Voltage Transfer Characteristics371

7.2.2 Noise Margins for the CMOS Inverter373

7.3 Dynamic Behavior of the CMOS Inverter375

7.3.1 Propagation Delay Estimate375

7.3.2 Rise and Fall Times377

7.3.3 Performance Scaling377

7.3.4 Delay of Cascaded Inverters379

7.4 Power Dissipation and Power Delay Product in CMOS380

7.4.1 Static Power Dissipation380

7.4.2 Dynamic Power Dissipation381

7.4.3 Power-Delay Product382

7.5 CMOS NOR and NAND Gates384

7.5.1 CMOS NOR Gate384

7.5.2 CMOS NAND Gates387

7.6 Design of Complex Gates in CMOS388

7.7 Minimum Size Gate Design and Performance393

7.8 Dynamic Domino CMOS Logic395

7.9 Cascade Buffers397

7.9.1 Cascade Buffer Delay Model397

7.9.2 Optimum Number of Stages398

7.10 The CMOS Transmission Gate400

7.11 CMOS Latchup401

Summary404

Key Terms405

References406

Problems406

CHAPTER 8 MOS MEMORY AND STORAGE CIRCUITS416

8.1 Random Access Memory417

8.1.1 Random Access Memory （RAM） Architecture417

8.1.2 A 256-Mb Memory Chip418

8.2 Static Memory Cells419

8.2.1 Memory Cell Isolation and Access—The 6-T Cell422

8.2.2 The Read Operation422

8.2.3 Writing Data into the 6-T Cell426

8.3 Dynamic Memory Cells428

8.3.1 The One-Transistor Cell430

8.3.2 Data Storage in the 1-T Cell430

8.3.3 Reading Data from the 1-T Cell431

8.3.4 The Four-Transistor Cell433

8.4 Sense Amplifiers434

8.4.1 A Sense Amplifier for the 6-T Cell434

8.4.2 A Sense Amplifier for the 1-T Cell436

8.4.3 The Boosted Wordline Circuit438

8.4.4 Clocked CMOS Sense Amplifiiers438

8.5 Address Decoders440

8.5.1 NOR Decoder440

8.5.2 NAND Decoder440

8.5.3 Decoders in Domino CMOS Logic443

8.5.4 Pass-Transistor Column Decoder443

8.6 Read-Only Memory （ROM）444

8.7 Flip-Flops447

8.7.1 RS Flip-Flop449

8.7.2 The D-Latch Using Transmission Gates450

8.7.3 A Master-Slave D Flip-Flop450

Summary451

Key Terms452

References452

Problems453

CHAPTER 9 BIPOLAR LOGIC CIRCUITS460

9.1 The Current Switch （Emitter-Coupled Pair）461

9.1.1 Mathematical Model for Static Behavior of the Current Switch462

9.1.2 Current Switch Analysis for V I ＞ VREF463

9.1.3 Current Switch Analysis for V I ＜ VREF464

9.2 The Emitter-Coupled Logic （ECL） Gate464

9.2.1 ECL Gate with vI = VH465

9.2.2 ECL Gate with vI = VL466

9.2.3 Input Current of the ECL Gate466

9.2.4 ECL Summary466

9.3 Noise Margin Analysis for the ECL Gate467

9.3.1 VI L，VOH，VI H，and VOL467

9.3.2 Noise Margins468

9.4 Current Source Implementation469

9.5 The ECL OR-NOR Gate471

9.6 The Emitter Follower473

9.6.1 Emitter Follower with a Load Resistor474

9.7 “Emitter Dotting” or “Wired-OR” Logic476

9.7.1 Parallel Connection of Emitter-Follower Outputs477

9.7.2 The Wired-OR Logic Function477

9.8 ECL Power-Delay Characteristics477

9.8.1 Power Dissipation477

9.8.2 Gate Delay479

9.8.3 Power-Delay Product480

9.9 Current Mode Logic481

9.9.1 CML Logic Gates481

9.9.2 CML Logic Levels482

9.9.3 VEE Supply Voltage482

9.9.4 Higher-Level CML483

9.9.5 CML Power Reduction484

9.9.6 NMOS CML485

9.10 The Saturating Bipolar Inverter487

9.10.1 Static Inverter Characteristics488

9.10.2 Saturation Voltage of the Bipolar Transistor488

9.10.3 Load-Line Visualization491

9.10.4 Switching Characteristics of the Saturated BJT491

9.11 A Transistor-Transistor Logic （TTL） Prototype494

9.11.1 TTL Inverter for vI = VL494

9.11.2 TTL Inverter for vI = VH495

9.11.3 Power in the Prototype TTL Gate496

9.11.4 VIH，VIL，and Noise Margins for the TTL Prototype496

9.11.5 Prototype Inverter Summary498

9.11.6 Fanout Limitations of the TTL Prototype498

9.12 The Standard 7400 Series TTL Inverter500

9.12.1 Analysis for V I = VL500

9.12.2 Analysis for V I = VH501

9.12.3 Power Consumption503

9.12.4 TTL Propagation Delay and Power-Delay Product503

9.12.5 TTL Voltage Transfer Characteristic and Noise Margins503

9.12.6 Fanout Limitations of Standard TTL504

9.13 Logic Functions in TTL504

9.13.1 Multi-Emitter Input Transistors505

9.13.2 TTL NAND Gates505

9.13.3 Input Clamping Diodes506

9.14 Schottky-Clamped TTL506

9.15 Comparison of the Power-Delay Products of ECL and TTL508

9.16 BiCMOS Logic508

9.16.1 BiCMOS Buffers509

9.16.2 BiNMOS Inverters511

9.16.3 BiCMOS Logic Gates513

Summary513

Key Terms515

References515

Additional Reading515

Problems516

PART THREE ANALOG ELECTRONICS527

CHAPTER10 ANALOG SYSTEMS AND IDEAL OPERATIONAL AMPLIFIERS529

10.1 An Example of an Analog Electronic System530

10.2 Amplifiication531

10.2.1 Voltage Gain532

10.2.2 Current Gain533

10.2.3 Power Gain533

10.2.4 The Decibel Scale534

10.3 Two-Port Models for Amplifiiers537

10.3.1 The g-parameters537

10.4 Mismatched Source and Load Resistances541

10.5 Introduction to Operational Amplifiers544

10.5.1 The Differential Amplifier544

10.5.2 Differential Amplifier Voltage Transfer Characteristic545

10.5.3 Voltage Gain545

10.6 Distortion in Amplifiers548

10.7 Differential Amplifier Model549

10.8 Ideal Differential and Operational Amplifiers551

10.8.1 Assumptions for Ideal Operational Amplifier Analysis551

10.9 Analysis of Circuits Containing Ideal Operational Amplifiiers552

10.9.1 The Inverting Amplifiier553

10.9.2 The Transresistance Amplifiier—A Current-to-Voltage Converter556

10.9.3 The Noninverting Amplifier558

10.9.4 The Unity-Gain Buffer，or Voltage Follower561

10.9.5 The Summing Amplifiier563

10.9.6 The Difference Amplifier565

10.10 Frequency-Dependent Feedback568

10.10.1 Bode Plots568

10.10.2 The Low-Pass Amplifier568

10.10.3 The High-Pass Amplifier572

10.10.4 Band-Pass Amplifiers575

10.10.5 An Active Low-Pass Filter578

10.10.6 An Active High-Pass Filter581

10.10.7 The Integrator582

10.10.8 The Differentiator586

Summary586

Key Terms588

References588

Additional Reading589

Problems589

CHAPTER 11 NONIDEAL OPERATIONAL AMPLIFIERS AND FEEDBACK AMPLIFIER STABILITY600

11.1 Classic Feedback Systems601

11.1.1 Closed-Loop Gain Analysis602

11.1.2 Gain Error602

11.2 Analysis of Circuits Containing Nonideal Operational Amplifiers603

11.2.1 Finite Open-Loop Gain603

11.2.2 Nonzero Output Resistance606

11.2.3 Finite Input Resistance610

11.2.4 Summary of Nonideal Inverting and Noninverting Amplifiiers614

11.3 Series and Shunt Feedback Circuits615

11.3.1 Feedback Amplifier Categories615

11.3.2 Voltage Amplifiers—Series-Shunt Feedback616

11.3.3 Transimpedance Amplifiers—Shunt-Shunt Feedback616

11.3.4 Current Amplifiiers—Shunt-Series Feedback616

11.3.5 Transconductance Amplifiiers—Series-Series Feedback616

11.4 Unifiied Approach to Feedback Amplifier Gain Calculation616

11.4.1 Closed-Loop Gain Analysis617

11.4.2 Resistance Calculation Using Blackman’S Theorem617

11.5 Series-Shunt Feedback-Voltage Amplifiiers617

11.5.1 Closed-Loop Gain Calculation618

11.5.2 Input Resistance Calculation618

11.5.3 Output Resistance Calculation619

11.5.4 Series-Shunt Feedback Amplifiier Summary620

11.6 Shunt-Shunt Feed back—Transresistance Amplifiers624

11.6.1 Closed-Loop Gain Calculation625

11.6.2 Input Resistance Calculation625

11.6.3 Output Resistance Calculation625

11.6.4 Shunt-Shunt Feedback Amplifier Summary626

11.7 Series-Series Feedback —Transconductance Amplifiiers629

11.7.1 Closed-Loop Gain Calculation630

11.7.2 Input Resistance Calculation630

11.7.3 Output Resistance Calculation631

11.7.4 Series-Series Feedback Amplifiier Summary631

11.8 Shunt-Series Feedback—Current Amplifiers633

11.8.1 Closed-Loop Gain Calculation634

11.8.2 Input Resistance Calculation635

11.8.3 Output Resistance Calculation635

11.8.4 Series-Series Feedback Amplifiier Summary635

11.9 Finding the Loop Gain Using Successive Voltage and Current Injection638

11.9.1 Simplifications641

11.10 Distortion Reduction Through the Use of Feedback641

11.11 DC Error Sources and Output Range Limitations642

11.11.1 Input-Offset Voltage643

11.11.2 Offset-Voltage Adjustment644

11.11.3 Input-Bias and Offset Currents645

11.11.4 Output Voltage and Current Limits647

11.12 Common-Mode Rejection and Input Resistance650

11.12.1 Finite Common-Mode Rejection Ratio650

11.12.2 Why Is CMRR Important？651

11.12.3 Voltage-Follower Gain Error Due to CMRR654

11.12.4 Common-Mode Input Resistance656

11.12.5 An Alternate Interpretation of CMRR657

11.12.6 Power Supply Rejection Ratio657

11.13 Frequency Response and Bandwidth of Operational Amplifiers659

11.13.1 Frequency Response of the NoninvertingAmplifiier661

11.13.2 Inverting Amplifiier Frequency Response664

11.13.3 Using Feedback to Control Frequency Response666

11.13.4 Large-Signal Limitations—Slew Rate and Full-Power Bandwidth668

11.13.5 Macro Model for Operational Amplifier Frequency Response669

11.13.6 Complete Op Amp Macro Models in SPICE670

11.13.7 Examples of Commercial General-Purpose Operational Amplifiiers670

11.14 Stability of Feedback Amplifiers671

11.14.1 The Nyquist Plot671

11.14.2 First-Order Systems672

11.14.3 Second-Order Systems and Phase Margin673

11.14.4 Step Response and Phase Margin674

11.14.5 Third-Order Systems and Gain Margin677

11.14.6 Determining Stability from the Bode Plot678

Summary682

Key Terms684

References684

Problems685

CHAPTER 12 OPERATIONAL AMPLIFIER APPLICATIONS697

12.1 Cascaded Amplifiiers698

12.1.1 Two-Port Representations698

12.1.2 Amplifiier Terminology Review700

12.1.3 Frequency Response of Cascaded Amplifiiers703

12.2 The Instrumentation Amplifiier711

12.3 Active Filters714

12.3.1 Low-Pass Filter714

12.3.2 A High-Pass Filter with Gain718

12.3.3 Band-Pass Filter720

12.3.4 The Tow-Thomas Biquad722

12.3.5 Sensitivity726

12.3.6 Magnitude and Frequency Scaling727

12.4 Switched-Capacitor Circuits728

12.4.1 A Switched-Capacitor Integrator728

12.4.2 Noninverting SC Integrator730

12.4.3 Switched-Capacitor Filters732

12.5 Digital-to-Analog Conversion733

12.5.1 D/A Converter Fundamentals733

12.5.2 D/A Converter Errors734

12.5.3 Digital-to-Analog Converter Circuits737

12.6 Analog-to-Digital Conversion740

12.6.1 A/D Converter Fundamentals741

12.6.2 Analog-to-Digital Converter Errors742

12.6.3 Basic A/D Conversion Techniques743

12.7 Oscillators754

12.7.1 The Barkhausen Criteria for Oscillation754

12.7.2 Oscillators Employing Frequency-Selective RC Networks755

12.8 Nonlinear Circuit Applications760

12.8.1 A Precision Half-Wave Rectifiier760

12.8.2 Nonsaturating Precision-Rectifiier Circuit761

12.9 Circuits Using Positive Feedback763

12.9.1 The Comparator and Schmitt Trigger763

12.9.2 The Astable Multivibrator765

12.9.3 The Monostable Multivibrator or One Shot766

Summary770

Key Terms772

Additional Reading773

Problems773

CHAPTER 13 SMALL-SIGNAL MODELING AND LINEAR AMPLIFICATION786

13.1 The Transistor as an Amplifier787

13.1.1 The BJT Amplifier788

13.1.2 The MOSFET Amplifier789

13.2 Coupling and Bypass Capacitors790

13.3 Circuit Analysis Using dc and ac Equivalent Circuits792

13.3.1 Menu for dc and ac Analysis792

13.4 Introduction to Small-Signal Modeling796

13.4.1 Graphical Interpretation of the Small-Signal Behavior of the Diode796

13.4.2 Small-Signal Modeling of the Diode797

13.5 Small-Signal Models for Bipolar Junction Transistors799

13.5.1 The Hybrid-Pi Model801

13.5.2 Graphical Interpretation of the Transconductance802

13.5.3 Small-Signal Current Gain802

13.5.4 The Intrinsic Voltage Gain of the BJT803

13.5.5 Equivalent Forms of the Small-Signal Model804

13.5.6 Simplifiied Hybrid Pi Model805

13.5.7 Definition of a Small Signal for the Bipolar Transistor805

13.5.8 Small-Signal Model for the pnp Transistor807

13.5.9 ac Analysis Versus Transient Analysis in SPICE807

13.6 The Common-Emitter （C-E） Amplifier808

13.6.1 Terminal Voltage Gain809

13.6.2 Input Resistance809

13.6.3 Signal Source Voltage Gain810

13.7 Important Limits and Model Simplifications810

13.7.1 A Design Guide for the Common-Emitter Amplifier810

13.7.2 Upper Bound on the Common-Emitter Gain812

13.7.3 Small-Signal Limit for the Common-emitter Amplifier812

13.8 Small-Signal Models for Field-Effect Transistors815

13.8.1 Small-Signal Model for the MOSFET815

13.8.2 Intrinsic Voltage Gain of the MOSFET817

13.8.3 Defiinition of Small-Signal Operation for the MOSFET817

13.8.4 Body Effect in the Four-Terminal MOSFET818

13.8.5 Small-Signal Model for the PMOS Transistor819

13.8.6 Small-Signal Model for the Junction Field-Effect Transistor820

13.9 Summary and Comparison of the Small-Signal Models of the BJT and FET821

13.10 The Common-Source Amplifier824

13.10.1 Common-Source Terminal Voltage Gain825

13.10.2 Signal Source Voltage Gain for the Common-Source Amplifier825

13.10.3 A Design Guide for the Common-Source Amplifier826

13.10.4 Small-Signal Limit for the Common-Source Amplifier827

13.10.5 Input Resistances of the Common-Emitter and Common-Source Amplifiers829

13.10.6 Common-Emitter and Common-Source Output Resistances832

13.10.7 Comparison of the Three Amplifier Resistances838

13.11 Common-Emitter and Common-Source Amplifier Summary838

13.11.1 Guidelines for Neglecting the Transistor Output Resistance839

13.12 Amplifier Power and Signal Range839

13.12.1 Power Dissipation839

13.12.2 Signal Range840

Summary843

Key Terms844

Problems845

CHAPTER 14 SINGLE-TRANSISTOR AMPLIFIERS857

14.1 Amplifier Classification858

14.1.1 Signal Injection and Extraction—The BJT858

14.1.2 Signal Injection and Extraction—The FET859

14.1.3 Common-Emitter （C-E） and Common-Source （C-S） Amplifiers860

14.1.4 Common-Collector （C-C） and Common-Drain （C-D） Topologies861

14.1.5 Common-Base （C-B） and Common-Gate （C-G） Amplifiers863

14.1.6 Small-Signal Model Review864

14.2 Inverting Amplifiers—Common-Emitter and Common-Source Circuits864

14.2.1 The Common-Emitter （C-E） Amplifier864

14.2.2 Common-Emitter Example Comparison877

14.2.3 The Common-Source Amplifier877

14.2.4 Small-Signal Limit for the Common-Source Amplifiier880

14.2.5 Common-Emitter and Common-Source Amplifier Characteristics884

14.2.6 C-E/C-S Amplifier Summary885

14.2.7 Equivalent Transistor Representation of the Generalized C-E/C-S Transistor885

14.3 Follower Circuits—Common-Collector and Common-Drain Amplifiers886

14.3.1 Terminal Voltage Gain886

14.3.2 Input Resistance887

14.3.3 Signal Source Voltage Gain888

14.3.4 Follower Signal Range888

14.3.5 Follower Output Resistance889

14.3.6 Current Gain890

14.3.7 C-C/C-D Amplifier Summary890

14.4 NoninvertingAmplifiers—Common-Base and Common-Gate Circuits894

14.4.1 Terminal Voltage Gain and Input Resistance895

14.4.2 Signal Source Voltage Gain896

14.4.3 Input Signal Range897

14.4.4 Resistance at the Collector and Drain Terminals897

14.4.5 Current Gain898

14.4.6 Overall Input and Output Resistances for the Noninverting Amplifiers899

14.4.7 C-B/C-G Amplifier Summary902

14.5 Amplifier Prototype Review and Comparison903

14.5.1 The BJT Amplifiiers903

14.5.2 The FET Amplifiiers905

14.6 Common-Source Amplifiers Using MOS Inverters907

14.6.1 Voltage Gain Estimate908

14.6.2 Detailed Analysis909

14.6.3 Alternative Loads910

14.6.4 Input and Output Resistances911

14.7 Coupling and Bypass Capacitor Design914

14.7.1 Common-Emitter and Common-Source Amplifiers914

14.7.2 Common-Collector and Common-Drain Amplifiers919

14.7.3 Common-Base and Common-Gate Amplifiers921

14.7.4 Setting Lower Cutoff Frequency f L924

14.8 Amplifiier Design Examples925

14.8.1 Monte Carlo Evaluation of the Common-Base Amplifier Design934

14.9 Multistage ac-Coupled Amplifiers939

14.9.1 A Three-Stage ac-Coupled Amplifiier939

14.9.2 Voltage Gain941

14.9.3 Input Resistance943

14.9.4 Signal Source Voltage Gain943

14.9.5 Output Resistance943

14.9.6 Current and Power Gain944

14.9.7 Input Signal Range945

14.9.8 Estimating the Lower Cutoff Frequency of the Multistage Amplifier948

Summary950

Key Terms951

Additional Reading952

Problems952

CHAPTER 15 DIFFERENTIAL AMPLIFIERS AND OPERATIONAL AMPLIFIER DESIGN968

15.1 Differential Amplifiers969

15.1.1 Bipolar and MOS Differential Amplifiiers969

15.1.2 dc Analysis of the Bipolar Differential Amplifiier970

15.1.3 Transfer Characteristic for the Bipolar Differential Amplifier972

15.1.4 ac Analysis of the Bipolar Differential Amplifier973

15.1.5 Differential-Mode Gain and Input and Output Resistances974

15.1.6 Common-Mode Gain and Input Resistance976

15.1.7 Common-Mode Rejection Ratio （CMRR）978

15.1.8 Analysis Using Differential- and Common-Mode Half-Circuits979

15.1.9 Biasing with Electronic Current Sources982

15.1.10 Modeling the Electronic Current Source in SPICE983

15.1.11 dc Analysis of the MOSFET Differential Amplifier983

15.1.12 Differential-Mode Input Signals985

15.1.13 Small-Signal Transfer Characteristic for the MOS Differential Amplifiier986

15.1.14 Common-Mode Input Signals986

15.1.15 Two-Port Model for Differential Pairs987

15.2 Evolution to Basic Operational Amplifiiers991

15.2.1 A Two-Stage Prototype for an Operational Amplifier992

15.2.2 Improving the Op Amp Voltage Gain997

15.2.3 Output Resistance Reduction998

15.2.4 A CMOS Operational Amplifiier Prototype1002

15.2.5 BiCMOS Amplifiers1004

15.2.6 All Transistor Implementations1004

15.3 Output Stages1006

15.3.1 The Source Follower—A Class-A Output Stage1006

15.3.2 Efficiency of Class-A Amplifiers1007

15.3.3 Class-B Push-Pull Output Stage1008

15.3.4 Class-AB Amplifiers1010

15.3.5 Class-AB Output Stages for Operational Amplifiers1011

15.3.6 Short-Circuit Protection1011

15.3.7 Transformer Coupling1013

15.4 Electronic Current Sources1016

15.4.1 Single-Transistor Current Sources1017

15.4.2 Figure of Merit for Current Sources1017

15.4.3 Higher Output Resistance Sources1018

15.4.4 Current Source Design Examples1018

Summary1027

Key Terms1028

References1029

Additional Reading1029

Problems1029

CHAPTER 16 ANALOG INTEGRATED CIRCUIT DESIGN TECHNIQUES1046

16.1 Circuit Element Matching1047

16.2 Current Mirrors1049

16.2.1 dc Analysis of the MOS Transistor Current Mirror1049

16.2.2 Changing the MOS Mirror Ratio1051

16.2.3 dc Analysis of the Bipolar Transistor Current Mirror1052

16.2.4 Altering the BJT Current Mirror Ratio1054

16.2.5 Multiple Current Sources1055

16.2.6 Buffered Current Mirror1056

16.2.7 Output Resistance of the Current Mirrors1057

16.2.8 Two-Port Model for the Current Mirror1058

16.2.9 The Widlar Current Source1060

16.2.10 The MOS Version of the Widlar Source1063

16.3 High-Output-Resistance Current Mirrors1063

16.3.1 The Wilson Current Sources1064

16.3.2 Output Resistance of the Wilson Source1065

16.3.3 Cascode Current Sources1066

16.3.4 Output Resistance of the Cascode Sources1067

16.3.5 Regulated Cascode Current Source1068

16.3.6 Current Mirror Summary1069

16.4 Reference Current Generation1072

16.5 Supply-Independent Biasing1073

16.5.1 A VBE-Based Reference1073

16.5.2 The Widlar Source1073

16.5.3 Power-Supply-Independent Bias Cell1074

16.5.4 A Supply-Independent MOS Reference Cell1075

16.6 The Bandgap Reference1077

16.7 The Current Mirror As an Active Load1081

16.7.1 CMOS Differential Amplifier with Active Load1081

16.7.2 Bipolar Differential Amplifier with Active Load1088

16.8 Active Loads in Operational Amplifiers1092

16.8.1 CMOS Op Amp Voltage Gain1092

16.8.2 dc Design Considerations1093

16.8.3 Bipolar Operational Amplifiers1095

16.8.4 Input Stage Breakdown1096

16.9 The μA741 Operational Amplifier1097

16.9.1 Overall Circuit Operation1097

16.9.2 Bias Circuitry1098

16.9.3 dc Analysis of the 741 Input Stage1099

16.9.4 ac Analysis of the 741 Input Stage1102

16.9.5 Voltage Gain of the Complete Amplifier1103

16.9.6 The 741 Output Stage1107

16.9.7 Output Resistance1109

16.9.8 Short Circuit Protection1109

16.9.9 Summary of the μA741 Operational Amplifiier Characteristics1109

16.10 The Gilbert Analog Multiplier1110

Summary1112

Key Terms1113

References1114

Problems1114

CHAPTER 17 AMPLIFIER FREQUENCY RESPONSE1128

17.1 Amplifier Frequency Response1129

17.1.1 Low-Frequency Response1130

17.1.2 Estimating ωL in the Absence of a Dominant Pole1130

17.1.3 High-Frequency Response1133

17.1.4 Estimating ωH in the Absence of a Dominant Pole1133

17.2 Direct Determination of the Low-Frequency Poles and Zeros—The Common-Source Amplifiier1134

17.3 Estimation of ωL Using the Short-Circuit Time-Constant Method1139

17.3.1 Estimate of ωL for the Common-Emitter Amplifier1140

17.3.2 Estimate of ωL for the Common-Source Amplifier1144

17.3.3 Estimate of ωL for the Common-Base Amplifier1145

17.3.4 Estimate of ωL for the Common-Gate Amplifier1146

17.3.5 Estimate of ωL for the Common-CollectorAmplifier1147

17.3.6 Estimate of ωL for the Common-Drain Amplifier1147

17.4 Transistor Models at High Frequencies1148

17.4.1 Frequency-Dependent Hybrid-Pi Model for the Bipolar Transistor1148

17.4.2 Modeling Cπ and Cμ in SPICE1149

17.4.3 Unity-Gain Frequency fT1149

17.4.4 High-Frequency Model for the FET1152

17.4.5 Modeling CGs and CGD in SPICE1153

17.4.6 Channel Length Dependence of fT1153

17.4.7 Limitations of the High-Frequency Models1155

17.5 Base Resistance in the Hybrid-Pi Model1155

17.5.1 Effect of Base Resistance on Midband Amplifiers1156

17.6 High-Frequency Common-Emitter and Common-Source Amplifier Analysis1158

17.6.1 The Miller Effect1159

17.6.2 Common-Emitter and Common-Source Amplifier High-Frequency Response1160

17.6.3 Direct Analysis of the Common-Emitter Transfer Characteristic1162

17.6.4 Poles of the Common-Emitter Amplifier1163

17.6.5 Dominant Pole for the Common-Source Amplifier1166

17.6.6 Estimation of ωH Using the Open-Circuit Time-Constant Method1167

17.6.7 Common-Source Amplifiier with Source Degeneration Resistance1170

17.6.8 Poles of the Common-Emitter with Emitter Degeneration Resistance1172

17.7 Common-Base and Common-Gate Amplifier High-Frequency Response1174

17.8 Common-Collector and Common-Drain Amplifier High-Frequency Response1177

17.9 Single-Stage Amplifiier High-Frequency Response Summary1179

17.9.1 Amplifier Gain-Bandwidth Limitations1180

17.10 Frequency Response of Multistage Amplifiiers1181

17.10.1 Differential Amplifier1181

17.10.2 The Common-Collector/Common-Base Cascade1182

17.10.3 High-Frequency Response of the Cascode Amplifier1184

17.10.4 Cutoff Frequency for the Current Mirror1185

17.10.5 Three-Stage Amplifier Example1187

17.11 Introduction to Radio Frequency Circuits1193

17.11.1 Radio Frequency Amplifiiers1194

17.11.2 The Shunt-Peaked Amplifier1194

17.11.3 Single-Tuned Amplifier1197

17.11.4 Use of a Tapped Inductor—The Auto Transformer1199

17.11.5 Multiple Tuned Circuits—Synchronous and Stagger Tuning1201

17.11.6 Common-Source Amplifier with Inductive Degeneration1202

17.12 Mixers and Balanced Modulators1205

17.12.1 Introduction to Mixer Operation1205

17.12.2 A Single-Balanced Mixer1206

17.12.3 The Differential Pair as a Single-Balanced Mixer1207

17.12.4 A Double-Balanced Mixer1208

17.12.5 The Gilbert Multiplier as a Double-Balanced Mixer/Modulator1210

Summary1213

Key Terms1215

Reference1215

Problems1215

CHAPTER18 TRANSISTOR FEEDBACK AMPLIFIERS AND OSCILLATORS1228

18.1 Basic Feedback System Review1229

18.1.1 Closed-Loop Gain1229

18.1.2 Closed-Loop impedances1230

18.1.3 Feedback Effects1230

18.2 Feedback Amplifier Analysis at Midband1232

18.3 Feedback Amplifier Circuit Examples1234

18.3.1 Series-Shunt Feedback—Voltage Amplifiers1234

18.3.2 Differential Input Series-Shunt Voltage Amplifier1239

18.3.3 Shunt-Shunt Feedback —Transresistance Amplifiers1242

18.3.4 Series-Series Feedback —Transconductance Amplifiers1248

18.3.5 Shunt-Series Feedback—Current Amplifiers1251

18.4 Review of Feedback Amplifier Stability1254

18.4.1 Closed-Loop Response of the Uncompensated Amplifier1254

18.4.2 Phase Margin1256

18.4.3 Higher-Order Effects1259

18.4.4 Response of the Compensated Amplifier1260

18.4.5 Small-Signal Limitations1262

18.5 Single-Pole Operational Amplifiier Compensation1262

18.5.1 Three-Stage Op Amp Analysis1263

18.5.2 Transmission Zeros in FET Op Amps1265

18.5.3 Bipolar Amplifier Compensation1266

18.5.4 Slew Rate of the Operational Amplifier1266

18.5.5 Relationships Between Slew Rate and Gain-Bandwidth Product1268

18.6 High-Frequency Oscillators1277

18.6.1 The Colpitts Oscillator1278

18.6.2 The Hartley Oscillator1279

18.6.3 Amplitude Stabilization in LC Oscillators1280

18.6.4 Negative Resistance in Oscillators1280

18.6.5 Negative GM Oscillator1281

18.6.6 Crystal Oscillators1283

Summary1287

Key Terms1289

References1289

Problems1289

APPENDIXES1300

A Standard Discrete Component Values1300

B Solid-State Device Models and SPICE Simulation Parameters1303

C Two-Port Review1310

Index1313