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数字设计 原理与实践 英文PDF|Epub|txt|kindle电子书版本网盘下载
- John F. Wakerly 著
- 出版社： 北京：高等教育出版社
- ISBN：7040100428
- 出版时间：2001
- 标注页数：946页
- 文件大小：69MB
- 文件页数：971页
- 主题词：
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图书目录
1 INTRODUCTION1
1.1 About Digital Design1
1.2 Analog versus Digital3
1.3 Digital Devices6
1.4 Electronic Aspects of Digital Design7
1.5 Software Aspects of Digital Design9
1.6 Integrated Circuits12
FOREWORD15
1.7 Programmable Logic Devices15
1.8 Application-Specific ICs16
PREFACE17
1.9 Printed-Circuit Boards18
1.10 Digital-Design Levels18
1.11 The Name of the Game22
1.12 Going Forward23
Drill Problems24
2 NUMBER SYSTEMS AND CODES25
2.1 Positional Number Systems26
2.2 Octal and Hexadecimal Numbers27
2.3 General Positional-Number-System Conversions29
2.4 Addition and Subtraction of Nondecimal Numbers32
2.5 Representation of Negative Numbers34
2.6 Two s-Complement Addition and Subtraction39
2.7 Ones -Complement Addition and Subtraction44
2.8 Binary Multiplication45
2.9 Binary Division47
2.10 Binary Codes for Decimal Numbers48
2.11 Gray Code51
2.12 Character Codes53
2.13 Codes for Actions, Conditions, and States53
2.14 n-Cubes and Distance57
2.15 Codes for Detecting and Correcting Errors58
2.16 Codes for Serial Data Transmission and Storage69
References73
Drill Problems74
Exercises76
3 DIGITAL CIRCUITS79
3.1 Logic Signals and Gates80
3.2 Logic Families84
3.3 CMOS Logic86
3.4 Electrical Behavior of CMOS Circuits96
3.5 CMOS Steady-State Electrical Behavior99
3.6 CMOS Dynamic Electrical Behavior113
3.7 Other CMOS Input and Output Structures123
3.8 CMOS Logic Families135
3.9 Bipolar Logic145
3.10 Transistor-Transistor Logic156
3.11 TTL Families166
3.12 CMOS/TTL Interfacing170
3.13 Low-Voltage CMOS Logic and Interfacing171
3.14 Emitter-Coupled Logic175
References183
Drill problems184
Exercises188
4 COMBINATIONAL LOGIC DESIGN PRINCIPLES193
4.1 Switching Algebra194
4.2 Combinational-Circuit Analysis209
4.3 Combinational-Circuit Synthesis215
4.4 Programmed Minimization Methods236
4.5 Timing Hazards244
4.6 The ABEL Hardware Description Language249
4.7 The VHDL Hardware Description Language264
References298
Drill Problems301
Exercises304
5 COMBINATIONAL LOGIC DESIGN PRACTICES311
5.1 Documentation Standards312
5.2 Circuit Timing330
5.3 Combinational PLDs337
5.4 Decoders351
5.5 Encoders376
5.6 Three-State Devices385
5.7 Multiplexers398
5.8 Exclusive-OR Gates and Parity Circuits410
5.9 Comparators419
5.10 Adders, Subtractors, and ALUs430
5.11 Combinational Multipliers446
References455
Drill Problems456
Exercises459
6 COMBINATIONAL-CIRCUIT DESIGN EXAMPLES467
6.1 Building-Block Design Examples468
6.2 Design Examples Using ABEL and PLDs479
6.3 Design Examples Using VHDL500
Exercises527
7 SEQUENTIAL LOGIC DESIGN PRINCIPLES529
7.1 Bistable Elements531
7.2 Latches and Flip-Flops534
7.3 Clocked Synchronous State-Machine Analysis550
7.4 Clocked Synchronous State-Machine Design563
7.5 Designing State Machines Using State Diagrams584
7.6 State-Machine Synthesis Using Transition Lists591
7.7 Another State-Machine Design Example594
7.8 Decomposing State Machines602
7.9 Feedback Sequential Circuits604
7.10 Feedback Sequential-Circuit Design615
7.11 ABEL Sequential-Circuit Design Features627
7.12 VHDL Sequential-Circuit Design Features641
References644
Drill Problems646
Exercises650
8 SEQUENTIAL LOGIC DESIGN PRACTICES659
8.1 Sequential-Circuit Documentation Standards660
8.2 Latches and Flip-Flops666
8.3 Sequential PLDs681
8.4 Counters693
8.5 Shift Registers712
8.6 Iterative versus Sequential Circuits747
8.7 Synchronous Design Methodology750
8.8 Impediments to Synchronous Design757
8.9 Synchronizer Failure and Metastability764
References784
Drill Problems786
Exercises788
9 SEQUENTIAL-CIRCUIT DESIGN EXAMPLES795
9.1 Design Examples Using ABEL and PLDs796
9.2 Design Examples Using VHDL813
Exercises829
10 MEMORY, CPLDS, AND FPGAS831
10.1 Read-Only Memory832
10.2 Read/Write Memory854
10.3 Static RAM854
10.4 Dynamic RAM866
10.5 Complex Programmable Logic Devices872
10.6 Field-Programmable Gate Arrays882
References891
Drill Problems892
Exercises892
11 ADDITIONAL REAL-WORLD TOPICS895
11.1 Computer-Aided Design Tools895
11.2 Design for Testability902
11.3 Estimating Digital System Reliability908
11.4 Transmission Lines, Reflections, and Termination912
References920
INDEX923