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现代应用集成电路设计 英文版PDF|Epub|txt|kindle电子书版本网盘下载
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- 周电著 著
- 出版社: 北京:科学出版社
- ISBN:9787030317667
- 出版时间:2011
- 标注页数:394页
- 文件大小:36MB
- 文件页数:404页
- 主题词:集成电路-电路设计-英文
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图书目录
Chapter 1 Introduction1
1.1 History of Integrated Circuits2
1.2 Roadmap of IC Technology6
1.3 ASIC9
1.4 Design Flow11
1.5 CAD Tools13
1.6 An ASIC Design Project MSDAP17
1.7 How to Use This Book18
1.8 Summery19
1.9 Problems19
References20
Chapter 2 VLSI Design Perspective and Flow22
2.1 Introduction23
2.2 VLSI Technology Trend23
2.3 SoC26
2.4 Methodology for Custom and Semi-custom IC Design28
2.4.1 Gate array28
2.4.2 Standard cell30
2.4.3 FPGA32
2.5 Design Domain and Perspective34
2.6 Design Flow37
2.7 Design Task41
2.8 Summary43
2.9 Problems43
References44
Chapter 3 Specification Development46
3.1 Introduction47
3.2 An ASIC Project MSDAP48
3.3 An Overall View ofthe Specific Requirement50
3.3.1 The required computation method by the MSDAP50
3.3.2 Additional information for the specification53
3.4 The System Setting54
3.5 I/O Interface and Pins58
3.5.1 Pins and their assignments58
3.5.2 Signal format and waveform59
3.6 Other Issues of the Specification62
3.7 Summary62
3.8 Problems62
References64
Chapter 4 Architecture Design65
4.1 Introduction66
4.2 Datapath Structure67
4.2.1 Single processor sequential structure68
4.2.2 Multi-processor parallel structure71
4.3 Functional Blocks and IPs73
4.3.l IP core74
4.3.2 Functional blocks in the MSDAP architecture75
4.4 Time Budget and Scheduling79
4.5 A Sample Architecture of the MSDAP Project80
4.5.1 An architecture sample80
4.5.2 Time budget justification of the proposed architecture96
4.6 Summary98
4.7 Problems98
References99
Chapter 5 Logic and Circuit Design101
5.1 Introduction102
5.2 Combinational Logics103
5.2.1 Decoder103
5.2.2 Encoder106
5.2.3 Multiplexer108
5.2.4 Arithmetic logic blocks109
5.3 Sequential Logics123
5.3.1 Latch and flip-flop124
5.3.2 Shift register136
5.3.3 Counter138
5.3.4 FSM144
5.4 Datapath153
5.5 Asynchronous Circuit156
5.6 Summery156
5.7 Problems156
References158
Chapter 6 Physical Design159
6.1 Introduction160
6.2 Design Rules161
6.3 Floorplan166
6.4 Routing171
6.4.1 Global routing176
6.4 2 Local routing179
6.5 Physical Layout Verification181
6.5.1 DRC181
6.5.2 XOR check182
6.5.3 Antenna check182
6.5.4 ERC183
6.5.5 LVS check183
6.6 Clock Network184
6.7 Power Network187
6.8 Engineering Change Order189
6.9 Package191
6.10 Summary193
6.11 Problems194
References195
Chapter 7 Timing,Power,and Performance Analysis198
7.1 Introduction199
7.2 Buffer Insertion Mechanism200
7.3 Transistor and Gate Sizing203
7.3.1 Transistor sizing203
7.3.2 Buffer sizing203
7.3.3 Gate sizing205
7.4 Timing Analysis206
7.4.1 Static timing analysis207
7.4.2 DTA vs.STA210
7.4.3 Circuit simulation in STA210
7.5 Interconnect Model and Circuit Order Reduction211
7.5.1 Lumped RC vs.distributed RLC model211
7.5.2 Circuit order reduction212
7.6 Low Power Design216
7.7 Design for Manufacture219
7.8 High-level Synthesis225
7.9 Performance Bound Evaluation226
7.10 Summary229
7.11 Problems229
References230
Chapter 8 Verification and Testing233
8.1 Introduction234
8.2 Digital Circuits Test236
8.2.1 Fault modeling237
8.2.2 Fault simulation240
8.2.3 Test generation for combinational logic242
8.2.4 Test generation for sequential logic245
8.2.5 ATPG using TetraMAX250
8.3 BIST252
8.3.1 The concept of BIST252
8.3.2 TPG253
8.3.3 ORA260
8.3.4 BIST architectures266
8.4 Scan and Boundary Scan271
8.4.1 Digital DFT for scan271
8.4.2 Scan chains276
8.4.3 Digital boundary scan standard-IEEE 1149.1281
8.5 Summary286
8.6 Problems286
References289
Appendix A A MSDAP290
A.1 Introduction291
A.2 A MSDAP291
Appendix B A C-Program Implementing the Algorithm of the MSDAP298
B.1 Introduction299
B.2 The MSDAP Computation Method in C-Code299
Appendix C An FSM for the MSDAP Operation Mode313
C.1 Introduction314
C.2 An FSM for the Operation Mode and System Setting314
Appendix D A Sample Project MSDAP Report326
D.1 Introduction327
D.2 A Sample Project MSDAP Report327