计算机组成与嵌入式系统 英文版·第6版PDF|Epub|txt|kindle电子书版本网盘下载

计算机组成与嵌入式系统 英文版·第6版PDF格式电子书版下载

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Chapter 1 BASIC STRUCTURE OF COMPUTERS1

1.1 Computer Types2

1.2 Functional Units3

1.2.1 Input Unit4

1.2.2 Memory Unit4

1.2.3 Arithmetic and Logic Unit5

1.2.4 Output Unit6

1.2.5 Control Unit6

1.3 Basic Operational Concepts7

1.4 Number Representation and Arithmetic Operations9

1.4.1 Integers10

1.4.2 Floating-Point Numbers16

1.5 Character Representation17

1.6 Pefformance17

1.6.1 Technology17

1.6.2 Parallelism19

1.7 Historical Perspective19

1.7.1 The First Generation20

1.7.2 The Second Generation20

1.7 3 The Third Generation21

1.7.4 The Fourth Generation21

1.8 Concluding Remarks22

1.9 Solved Problems22

Problems24

References25

Chapter 2 INSTRUCTION SET ARCHITECTURE27

2.1 Memory Locations and Addresses28

2.1.1 Byte Addressability30

2.1.2 Big-Endian and Little-Endian Assignments30

2.1.3 Word Alignment31

2.1.4 Accessing Numbers and Characters32

2.2 Memory Operations32

2.3 Instructions and Instruction Sequencing32

2.3.1 Register Transfer Notation33

2.3.2 Assembly-Language Notation33

2.3.3 RISC and CISC Instruction Sets34

2.3.4 Introduction to RISC Instruction Sets34

2.3.5 Instruction Exeeution and Straight-Line Sequencing36

2.3.6 Branching37

2.3.7 Generating Memory Addresses40

2.4 Addressing Modes40

2.4.1 Implementation of Variables and Constants41

2.4.2 Indirection and Pointers42

2.4.3 Indexing and Atrays45

2.5 Assembly Language48

2.5.1 Assembler Directives50

2.5.2 Assembly and Execution of Programs53

2.5.3 Number Notation54

2.6 Stacks55

2.7 Subroutines56

2.7.1 Subroutine Nesting and the Processor Stack58

2.7.2 Parameter Passing59

2.7.3 The Stack Frame63

2.8 Additional Instructions65

2.8.1 Logic Instructions67

2.8.2 Shift and Rotate Instructions68

2.8.3 Multiplication and Division71

2.9 Dealing with 32-Bit Immediate Values73

2.10 CISC Instruction Sets74

2.10.1 AdditionalAddressing Modes75

2.10.2 Condition Codes77

2.11 RISC and CISC Styles78

2.12 Example Programs79

2.12.1 Vector Dot Product Program79

2.12.2 String Search Program81

2.1.3 Encoding of Machine Instructions82

2.1.4 Concluding Remarks85

2.1.5 Solved Problems85

Problems90

Chapter 3 BASIC INPUT/OUTPUT95

3.1 Accessing I/O Deviccs96

3.1.1 I/O Device Interface97

3.1.2 Program-Controlled I/O97

3.1.3 An Example of a RISC-Style I/O Program101

3.1.4 Au Example of a CISC-Style I/O Program101

3.2 Interrupts103

3.2.1 Enabling and Disabling Interrupts106

3.2.2 Handling Multiple Devices107

3.2.3 Controlling I/O Device Behavior109

3.2.4 Processor Control Registers110

3.2.5 Examples of Interrupt Programs111

3.2.6 Exceptions116

3.3 Concluding Remarks119

3.4 Solved Problems119

Problems126

Chapter 4 SOFTWARE129

4.1 The Assembly Process130

4.1.1 Two-pass Assembler131

4.2 Loading and Executing Object Programs131

4.3 The Linker132

4.4 Libraries133

4.5 The Compiler133

4.5.1 Compiler Optimizations134

4.5.2 Combining Programs Written in Different Languages134

4.6 The Debugger134

4.7 Using a High-level Language for I/O Tasks137

4.8 Interaction between Assembly Language and C Language139

4.9 The Operating System143

4.9.1 The Boot-strapping Process144

4.9.2 Managing the Execution of Application Programs144

4.9.3 Use of Interrupts in Operating Systems146

4.10 Concluding Remarks149

Problems149

References150

Chapter 5 BASIC PROCESSING UNIT151

5.1 Some Fundamental Concepts152

5.2 Instruction Execution155

5.2.1 Load Instructions155

5.2.2 Arithmetic and Logic Instructions156

5.2.3 Store Instructions157

5.3 Hardware Components158

5.3.1 Register File158

5.3.2 ALU160

5.3.3 Datapath161

5.3.4 Instruction Fetch Section164

5.4 Instruction Fetch and Execution Steps165

5.4.1 Branching168

5.4.2 Waiting for Memory171

5.5 Control Signals172

5.6 Hardwired Contol175

5.6.1 Datapath Contol Signals177

5.6.2 Dealing with Memory Delay177

5.7 CISC-Style Processors178

5.7 1 An Interconnect using Buses180

5.7.2 Microprogrammed Control183

5.8 Concluding Remarks185

5.9 Solved Problems185

Problems188

Chapter 6 PIPELINING193

6.1 Basic Concept—The Ideal Case194

6.2 Pipeline Organization195

6.3 Pipelining Issues196

6.4 Data Dependencies197

6.4.1 Operand Forwarding198

6.4.2 Handling Data Dependencies in Software199

6.5 Memory Delays201

6.6 Branch Delays202

6.6.1 Unconditional Branches202

6.6.2 Conditional Branches204

6.6 3 The Branch Delay Slot204

6.6.4 Branch Prediction205

6.7 Resource Limitations209

6.8 Performance Evaluation209

6.8.1 Effects of Stalls and Penalties210

6.8.2 Number of Pipeline Stages212

6.9 Superscalar Operation212

6.9.1 Branches and Data Dependencies214

6.9.2 Out-of-Order Execution215

6.9 3 Execution Completion216

6.9.4 Dispatch Operation217

6.10 Pipelining in CISC Processors218

6.10.1 Pipelining in ColdFire Processors219

6.10.2 Pipelining in Intel Processors219

6.11 Concluding Remarks220

6.12 Examples of Solved Problems220

Problems222

References226

Chapter 7 INPUT/OUTPUT ORGANIZATION227

7.1 Bus Structure228

7.2 Bus Operation229

7.2.1 Synchronous Bus230

7.2.2 Asynchronous Bus233

7.2.3 Electrical Considerations236

7.3 Arbitration237

7.4 Interface Circuits238

7.4.1 Parallel Interface239

7.4.2 Serial Interface243

7.5 Interconnection Standards247

7.5.1 Universal Serial Bus(USB)247

7.5.2 FireWire251

7.5.3 PCI Bus252

7.5.4 SCSI Bus256

7.5 5 SATA258

7.5.6 SAS258

7.5.7 PCI Express258

7.6 Concluding Remarks260

7.7 Solved Problems260

Problems263

References266

Chapter 8 THE MEMORY SYSTEM267

8.1 Basic Concepts268

8.2 Semiconductor RAM Memories270

8.2.1 Internal Organization of Memory Chips270

8.2.2 Static Memories271

8.2.3 Dynamic RAMs274

8.2.4 Synchronous DRAMs276

8.2.5 Structure of Larger Memories279

8.3 Read-only Memories282

8.3.1 ROM283

8.3.2 PROM283

8.3.3 EPROM284

8.3.4 EEPROM284

8.3.5 Flash Memory284

8.4 Direct Memory Access285

8.5 Memory Hierarchy288

8.6 Cache Memories289

8.6.1 Mapping Functions291

8.6.2 Replacement Algorithms296

8.6.3 Examples of Mapping Techniques297

8.7 Performance Considerations300

8.7.1 Hit Rate and Miss Penalty301

8.7.2 Caches on the Processor Chip302

8.7.3 Other Enhancements303

8.8 Virtual Memory305

8.8.1 Address Translation306

8.9 Memory Management Requirements310

8.10 Secondary Storage311

8.10.1 Magnetic Hard Disks311

8.10.2 Optical Disks317

8.10.3 Magnetic Tape Systems322

8.11 Concluding Remarks323

8.12 Solved Problems324

Problems328

References332

Chapter 9 ARITHMETIC335

9.1 Addition and Subtraction of Signed Numbers336

9.1.1 Addition/Subtraction Logic Unit336

9.2 Design of Fast Adders339

9.2.1 Cany-Lookahead Addition340

9.3 Multiplication of Unsigned Numbers344

9.3.1 Array Multiplier344

9.3.2 Sequential Cireuit Multiplier346

9.4 Multiplication of Signed Numbers346

9.4.1 The Booth Algorithm348

9.5 Fast Multiplication351

9.5.1 Bit-Pair Recoding of Multipliers352

9.5.2 Carry-Save Addition of Summands353

9.5.3 Summand Addition Tree using 3-2 Rexducers355

9.5.4 Summand Addition Tree using 4-2 Reducers357

9.5.5 Summary of Fast Multiplication359

9.6 Integer Division360

9.7 Floating-Point Numbers and Operations363

9.7.1 Arithmetic Operations on Floating-Point Numbers367

9.7.2 Guard Bits and Truneation368

9.7.3 Implementing Floating-Point Operations369

9.8 Decimal-to-Binary Conversion372

9.9 Concluding Remarks372

9.10 Solved Problems374

Problems377

References383

Chapter 10 EMBEDDED SYSTEMS385

10.1 Examples of Embedded Systems386

10.1.1 Microwave Oven386

10.1.2 Digital Camera387

10.1.3 HomeTelemetry390

10.2 Microcontroller Chips for Embedded Applications390

10.3 A Simple Microcontroller392

10.3.1 Parallel I/O Interface392

10.3.2 Serial I/O Interface395

10.3.3 Counter/Timer397

10.3.4 Interrupt-Control Mechanism399

10.3.5 Programming Examples399

10.4 Reaction Timer-A Complete Example401

10.5 Sensors and Actuators407

10.5.1 Sensors407

10.5.2 Actuators410

10.5.3 Application Examples411

10.6 Microcontroller Families412

10.6.1 Microcontrollers Based on the Intel 8051413

10.6.2 Freescale Microcontrollers413

10.6.3 ARM Microcontrollers414

10.7 Design Issues414

10.8 Concluding Remarks417

Problems418

References420

Chapter 11 SYSTEM-ON-A-CHIP-A CASE STUDY421

11.1 FPGAImplementation422

11.1.1 FpGADevices423

11.1.2 ProcessorChoice423

11.2 Computer-Aided Design Tools424

11.2.1 Altera CADTools425

11.3 Alarm Clock Example428

11.3 1 User's View of the System428

11.3.2 System Definition and Generation429

11.3.3 Circuit Implementation430

11.3.4 Application Software431

11.4 Concluding Remarks440

Problems440

References441

Chapter 12 PARALLEL PROCESSING AND PERFORMANCE443

12.1 Hardware Multithreading444

12.2 Vector(SIMD)Processing445

12.2.1 Graphics Processing Units(GPUs)448

12.3 Shared-Memory Multiprocessors448

12.3.1 Interconnection Networks450

12.4 Cache Coherence453

12.4.1 Write-Through Protocol453

12.4.2 Write-Back protocol454

12.4.3 Snoopy Caches454

12.4.4 Directory-Based Cache Coherence456

12.5 Message-Passing Multicomputers456

12.6 Parallel Programming for Multiprocessors456

12.7 Pefformance Modeling460

12.8 Concluding Remarks461

Problems462

References463

Appendix A LoGIC CIRCUITS465

A.1 Basic Logic Functions469

A.1.1 Electronic Logic Gates469

A.2 Synthesis of Logic Functions470

A.3 Minimization of Logic Expressions472

A.3.1 Minimization using Karnaugh Maps475

A.3.2 Don't-Care Conditions477

A.4 Synthesis with NAND and NOR Gates479

A.5 Practical Implementation of Logic Gates482

A.5.1 CMOS Circuits484

A.5.2 Propagation Delay489

A.5.3 Fan-In and Fan-Out Constraints490

A.5.4 Tri-State Buffers491

A.6 Flip-Flops492

A.6.1 Gated Latches493

A.6.2 Master-Slave Flip-Flop495

A.6.3 Edge Triggering498

A.6.4 TFlip-Flop498

A.6.5 JK Flip-Flop499

A.6.6 Flip-Flops with Preset and Clear501

A.7 Registers and Shift Registers502

A.8 Counters503

A.9 Decoders505

A.10 Multiplexers506

A.11 Programmable Logic Devices(PLDs)509

A.11.1 Programmable Logic Array(PLA)509

A.11.2 Programmable Array Logic(FAL)511

A.11.3 Complex Programmable Logic Devices(CPLDs)512

A.12 Field-Programmable Gate Arrays514

A.13 Sequential Circuits516

A.13.1 Design of an Up/Down Counter as a Sequential Circuit516

A 13.2 Timing Diagrams519

A.13.3 The Finite State Machine Model520

A.13.4 Synthesis of Finite State Machines521

A.14 Concluding Remarks522

Problems522

References528

Appndix B THE ALTERA NIOs Ⅱ PROCESSOR529

B.1 Nios Ⅱ Characteristics530

B.2 General-Purpose Registers531

B.3 Addressing Modes532

B.4 Instructions533

B.4.1 Notation533

B.4.2 Load and Store Instructions534

B.4.3 Arithmetic Instnctions536

B.4.4 Logic Instructions537

B.4.5 Move Instructions537

B.4.6 Branch and Jump Instructions538

B.4.7 Subroutine Linkage Instructions541

B.4.8 Comparison Instructions545

B.4.9 Shift Instructions546

B.4.10 Rotate Instructions547

B.4.11 Control Instructions548

B.5 Pseudoinstructions548

B.6 Assembler Directives549

B.7 Carry and Overflow Detection551

B.8 Example Programs553

B.9 Control Registers553

B.10 Input/Output555

B.10.1 Program-Controlled I/O556

B.10.2 Interrupts and Exceptions556

B.11 Advanced Configurations of Nios Ⅱ Processor562

B.11.1 External Interrupt Controller562

B.11.2 Memory Management Unit562

B.11.3 Floating-Point Hardware562

B.12 Concluding Remarks563

B.13 Solved Problems563

Problems568

Appendix C THE COLDFIRE PROCESSOR571

C.1 Memory Organization572

C.2 Registers572

C.3 Instructions573

C.3.1 Addressing Modes575

C.3.2 Move Instruction577

C.3.3 Arithmetic Instructions578

C.3.4 Branch and Jump Instructions582

C.3.5 Logic Instructious585

C.3.6 Shift Instructions586

C.3.7 Subroutine Linkage Instructions587

C.4 Assembler Directives593

C.5 Example Programs594

C.5.1 Vector Dot Product Program594

C.5.2 String Search Program595

C.6 Mode of Operation and Other Control Features596

C.7 Input/Output597

C.8 Floating-Point Operations599

C.8.1 FMOVE Instruction599

C.8.2 Floating-Point Arithmetic Instructions600

C.8.3 Comparison and Branch Instructions601

C.8.4 Additional Floating-Point Instructions601

C.8.5 Example Floating-Point Program602

C.9 Concluding Remarks603

C.10 Solved Problems603

Problems608

References609

Appendix D THE ARM PROCESSOR611

D.1 ARM Characteristics612

D.1.1 Unusual Aspects of the ARM Architecture612

D.2 Register Structure613

D.3 Addressing Modes614

D.3.1 Basic Indexed Addressing Mode614

D.3.2 Relative Addressing Mode615

D.3.3 Index Modes with Writeback616

D.3.4 Offset Determination616

D.3.5 Register,Immediate and Absolute Addressing Modes618

D 3.6 Addressing Mode Examples618

D.4 Instructions621

D.4.1 Load and Store Instructions621

D.4.2 Arithmetic Instructions622

D.4.3 Move Instructions625

D.4.4 Logic and Test Instructions626

D.4.5 Compare Instructions627

D.4.6 Setting Condition Code Flags628

D.4.7 Branch Instructions628

D.4.8 Subroutine Linkage Instructions631

D.5 Assembly Language635

D.5.1 Pseudoinstructions637

D.6 Example Programs638

D.6.1 Vector Dot Product639

D.6.2 String Search639

D.7 Operating Modes and Exceptions639

D.7.1 Banked Registers641

D.7.2 Exception Types642

D.7.3 System Mode644

D.7.4 Handling Exceptions644

D.8 Input/Output646

D.8.1 Program-Controlled I/O646

D.8.2 Interrupt-Driven I/O648

D.9 Conditional Execution of Instructions648

D.10 Coprocessors650

D.11 Embedded Applications and the Thumb ISA651

D.12 Concluding Remarks651

D.13 Solved Problems652

Problems657

References660

Appendix E THE INTEL IA-32 ARCHITECTURE661

E.1 Memory Organization662

E.2 Register Structure662

E.3 Addressing Modes665

E.4 Instructions668

E.4.1 Machine Instruction Format670

E.4.2 Assembly-Language Notation670

E.4.3 Move Instruction671

E.4.4 Load-Effective-Address Instruction671

E.4.5 Arithmetic Instructions672

E.4.6 Jump and Loop Instructions674

E.4.7 Logic Instructions677

E.4.8 Shift and Rotate Instructions678

E.4.9 Subroutine Linkage Instructions679

E.4.10 Operations on Large Numbers681

E.5 Assembler Directives685

E.6 Example Programs686

E.6.1 Vector Dot Product Program686

E.6.2 String Search Program686

E.7 Interrupts and Exceptions687

E.8 Input/Output Examples689

E.9 Scalar Floating-Point Operations690

E.9.1 Load and Store Instructions692

E.9.2 Arithmetic Instructions693

E.9.3 Comparison Instructions694

E.9.4 Additional Instructions694

E.9.5 Example Floating-Point Program694

E.10 Multimedia Extension(MMX)Operations695

E.11 Vector(SIMD)Floating-Point Operations696

E.12 Examples of Solved Problems697

E.13 Concluding Remarks702

Problems702

References703