数字集成电路设计 从VLSI体系结构到CMOS制造 英文版PDF|Epub|txt|kindle电子书版本网盘下载

数字集成电路设计 从VLSI体系结构到CMOS制造 英文版PDF格式电子书版下载

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Chapter 1 Introduction to Microelectronics1

1.1 Economic impact1

1.2 Concepts and terminology4

1.2.1 The Guinness book of records point of view4

1.2.2 The marketing point of view5

1.2.3 The fabrication point of view6

1.2.4 The design engineer's point of view10

1.2.5 The business point of view17

1.3 Design flow in digital VLSI18

1.3.1 The Y-chart,a map of digital electronic systems18

1.3.2 Major stages in VLSI design19

1.3.3 Cell libraries28

1.3.4 Electronic design automation software29

1.4 Field-programmable logic30

1.4.1 Configuration technologies30

1.4.2 Organization of hardware resources32

1.4.3 Commercial products35

1.5 Problems37

1.6 Appendix Ⅰ:A brief glossary of logic families38

1.7 Appendix Ⅱ:An illustrated glossary of circuit-related terms40

Chapter 2 From Algorithms to Architectures44

2.1 The goals of architecture design44

2.1.1 Agenda45

2.2 The architectural antipodes45

2.2.1 What makes an algorithm suitable for a dedicated VLSI architecture?50

2.2.2 There is plenty of land between the architectural antipodes53

2.2.3 Assemblies of general-purpose and dedicated processing units54

2.2.4 Coprocessors55

2.2.5 Application-specific instruction set processors55

2.2.6 Configurable computing58

2.2.7 Extendable instruction set processors59

2.2.8 Digest60

2.3 A transform approach to VLSI architecture design61

2.3.1 There is room for remodelling in the algorithmic domain62

2.3.2&and there is room in the architectural domain64

2.3.3 Systems engineers and VLSI designers must collaborate64

2.3.4 A graph-based formalism for describing processing algorithms65

2.3.5 The isomorphic architecture66

2.3.6 Relative merits of architectural alternatives67

2.3.7 Computation cycle versus clock period69

2.4 Equivalence transforms for combinational computations70

2.4.1 Common assumptions71

2.4.2 Iterative decomposition72

2.4.3 Pipelining75

2.4.4 Replication79

2.4.5 Time sharing81

2.4.6 Associativity transform　86

2.4.7 Other algebraic transforms87

2.4.8 Digest87

2.5 Options for temporary storage of data89

2.5.2 Available memory configurations and area occupation89

2.5.3 Storage capacities90

2.5.4 Wiring and the costs of going off-chip91

2.5.5 Latency and timing91

2.5.6 Digest92

2.6 Equivalence transforms for nonrecursive computations93

2.6.1 Retiming94

2.6.2 Pipelining revisited95

2.6.3 Systolic conversion97

2.6.4 Iterative decomposition and time-sharing revisited98

2.6.5 Replication revisited98

2.6.6 Digest99

2.7 Equivalence transforms for recursive computations99

2.7.1 The feedback bottleneck100

2.7.2 Unfolding of first-order loops101

2.7.3 Higher-order loops103

2.7.4 Time-variant loops105

2.7.5 Nonlinear or general loops106

2.7.6 Pipeline interleaving is not an equivalence transform109

2.7.7 Digest111

2.8 Generalizations of the transform approach112

2.8.1 Generalization to other levels of detail112

2.8.2 Bit-serial architectures113

2.8.3 Distributed arithmetic116

2.8.4 Generalization to other algebraic structures118

2.8.5 Digest121

2.9 Conclusions122

2.9.1 Summary122

2.9.2 The grand architectural alternatives from an energy point of view124

2.9.3 A guide to evaluating architectural alternatives126

2.10 Problems128

2.11 Appendix Ⅰ:A brief glossary of algebraic structures130

2.12 Appendix Ⅱ:Area and delay figures of VLSI subfunctions133

Chapter 3 Functional Verification136

3.1　How to establish valid functional specifications137

3.1.1 Formal specification138

3.1.2 Rapid prototyping138

3.2 Developing an adequate simulation strategy139

3.2.1 What does it take to uncover a design flaw during simulation?139

3.2.2 Stimulation and response checking must occur automatically140

3.2.3 Exhaustive verification remains an elusive goal142

3.2.4 All partial verification techniques have their pitfalls143

3.2.5 Collecting test cases from multiple sources helps150

3.2.6 Assertion-based verification helps150

3.2.7 Separating test development from circuit design helps151

3.2.8 Virtual prototypes help to generate expected responses153

3.3 Reusing the same functional gauge throughout the entire design cycle153

3.3.1 Alternative ways to handle stimuli and expected responses155

3.3.2 Modular testbench design156

3.3.3 A well-defined schedule for stimuli and responses156

3.3.4 Trimming run times by skipping redundant simulation sequences159

3.3.5 Abstracting to higher-level transactions on higher-level data160

3.3.6 Absorbing latency variations across multiple circuit models164

3.4 Conclusions166

3.5 Problems168

3.6 Appendix Ⅰ:Formal approaches to functional verification170

3.7 Appendix Ⅱ:Deriving a coherent schedule for simulation and test171

Chapter 4 Modelling Hardware with VHDL175

4.1 Motivation175

4.1.1 Why hardware synthesis?175

4.1.2 What are the alternatives to VHDL?176

4.1.3 What are the origins and aspirations of the IEEE 1076 standard?176

4.1.4 Why bother learning hardware description languages?179

4.1.5 Agenda180

4.2 Key concepts and constructs of VHDL180

4.2.1 Circuit hierarchy and connectivity181

4.2.2 Concurrent processes and process interaction185

4.2.3 A discrete replacement for electrical signals192

4.2.4 An event-based concept of time for governing simulation200

4.2.5 Facilities for model parametrization211

4.2.6 Concepts borrowed from programming languages216

4.3 Putting VHDL to service for hardware synthesis223

4.3.1 Synthesis overview223

4.3.2 Data types224

4.3.3 Registers,finite state machines,and other sequential subcircuits225

4.3.4 RAMs,ROMs,and other macrocells231

4.3.5 Circuits that must be controlled at the netlist level233

4.3.6 Timing constraints234

4.3.7 Limitations and caveats for synthesis238

4.3.8 How to establish a register transfer-level model step by step238

4.4 Putting VHDL to service for hardware simulation242

4.4.1 Ingredients of digital simulation242

4.4.2 Anatomy of a generic testbench242

4.4.3 Adapting to a design problem at hand245

4.4.4 The VITAL modelling standard IEEE 1076.4245

4.5 Conclusions247

4.6 Problems248

4.7 Appendix Ⅰ:Books and Web Pages on VHDL250

4.8 Appendix Ⅱ:Related extensions and standards251

4.8.1 Protected shared variables IEEE 1076a251

4.8.2 The analog and mixed-signal extension IEEE 1076.1252

4.8.3 Mathematical packages for real and complex numbers IEEE 1076.2253

4.8.4 The arithmetic packages IEEE 1076.3254

4.8.5 A language subset earmarked for synthesis IEEE 1076.6254

4.8.6 The standard delay format(SDF)IEEE 1497254

4.8.7 A handy compilation of type conversion functions255

4.9 Appendix Ⅲ:Examples of VHDL models256

4.9.1 Combinatiohal circuit models256

4.9.2 Mealy,Moore,and Medvedev machines261

4.9.3 State reduction and state encoding268

4.9.4 Simulation testbenches270

4.9.5 Working with VHDL tools from different vendors285

Chapter 5 The Case for Synchronous Design286

5.1 Introduction286

5.2 The grand alternatives for regulating state changes287

5.2.1 Synchronous clocking287

5.2.2 Asynchronous clocking288

5.2.3 Self-timed clocking288

5.3 Why a rigorous approach to clocking is essential in VLSI290

5.3.1 The perils of hazards290

5.3.2 The pros and cons of synchronous clocking291

5.3.3 Clock-as-clock-can is not an option in VLSI293

5.3.4 Fully self-timed clocking is not normally an option either294

5.3.5 Hybrid approaches to system clocking294

5.4 The dos and don'ts of synchronous circuit design296

5.4.1 First guiding principle:Dissociate signal classes!296

5.4.2 Second guiding principle:Allow circuits to settle before clocking!298

5.4.3 Synchronous design rules at a more detailed level298

5.5 Conclusions306

5.6 Problems306

5.7 Appendix:On identifying signals307

5.7.1 Signal class307

5.7.2 Active level308

5.7.3 Signaling waveforms309

5.7.4 Three-state capability311

5.7.5 Inputs,outputs,and bidirectional terminals311

5.7.6 Present state vs.next state312

5.7.7 Syntactical conventions312

5.7.8 A note on upper-and lower-case letters in VHDL313

5.7.9 A note on the portability of names across EDA platforms314

Chapter 6 Clocking of Synchronous Circuits315

6.1 What is the difficulty in clock distribution?315

6.1.1 Agenda316

6.1.2 Timing quantities related to clock distribution317

6.2 How much skew and jitter does a circuit tolerate?317

6.2.1 Basics317

6.2.2 Single-edge-triggered one-phase clocking319

6.2.3 Dual-edge-triggered one-phase clocking326

6.2.4 Symmetric level-sensitive two-phase clocking327

6.2.5 Unsymmetric level-sensitive two-phase clocking331

6.2.6 Single-wire level-sensitive two-phase clocking334

6.2.7 Level-sensitive one-phase clocking and wave pipelining336

6.3 How to keep clock skew within tight bounds339

6.3.1 Clock waveforms339

6.3.2 Collective clock buffers340

6.3.3 Distributed clock buffer trees343

6.3.4 Hybrid clock distribution networks344

6.3.5 Clock skew analysis345

6.4 How to achieve friendly input/output timing346

6.4.1 Friendly as opposed to unfriendly I/O timing346

6.4.2 Impact of clock distribution delay on I/O timing347

6.4.3 Impact of PTV variations on I/O timing349

6.4.4 Registered inputs and outputs350

6.4.5 Adding artificial contamination delay to data inputs350

6.4.6 Driving input registers from an early clock351

6.4.7 Tapping a domain's clock from the slowest component therein351

6.4.8 "Zero-delay"clock distribution by way of a DLL or PLL352

6.5 How to implement clock gating properly353

6.5.1 Traditional feedback-type registers with enable353

6.5.2 A crude and unsafe approach to clock gating354

6.5.3 A simple clock gating scheme that may work under certain conditions355

6.5.4 Safe clock gating schemes355

6.6 Summary357

6.7 Problems361

Chapter 7 Acquisition of Asynchronous Data364

7.1 Motivation364

7.2 The data consistency problem of vectored acquisition366

7.2.1 Plain bit-parallel synchronization366

7.2.2 Unit-distance coding367

7.2.3 Suppression of crossover patterns368

7.2.4 Handshaking369

7.2.5 Partial handshaking371

7.3 The data consistency problem of scalar acquisition373

7.3.1 No synchronization whatsoever373

7.3.2 Synchronization at multiple places373

7.3.3 Synchronization at a single place373

7.3.4 Synchronization from a slow clock374

7.4 Metastable synchronizer behavior374

7.4.1 Marginal triggering and how it becomes manifest374

7.4.2 Repercussions on circuit functioning378

7.4.3 A statistical model for estimating synchronizer reliability379

7.4.4 Plesiochronous interfaces381

7.4.5 Containment of metastable behavior381

7.5 Summary384

7.6 Problems384

Chapter 8 Gate-and Transistor-Level Design386

8.1 CMOS logic gates386

8.1.1 The MOSFET as a switch387

8.1.2 The inverter388

8.1.3 Simple CMOS gates396

8.1.4 Composite or complex gates399

8.1.5 Gates with high-impedance capabilities403

8.1.6 Parity gates406

8.1.7 Adder slices407

8.2 CMOS bistables409

8.2.1 Latches410

8.2.2 Function latches412

8.2.3 Single-edge-triggered flip-flops413

8.2.4 The mother of all flip-flops415

8.2.5 Dual-edge-triggered flip-flops417

8.2.6 Digest418

8.3 CMOS on-chip memories418

8.3.1 Static RAM418

8.3.2 Dynamic RAM423

8.3.3 Other differences and commonalities424

8.4 Electrical CMOS contraptions425

8.4.1 Snapper425

8.4.2 Schmitt trigger426

8.4.3 Tie-off cells427

8.4.4 Filler cell or fillcap428

8.4.5 Level shifters and input/output buffers429

8.4.6 Digitally adjustable delay lines429

8.5 Pitfalls430

8.5.1 Busses and three-state nodes430

8.5.2 Transmission gates and other bidirectional components434

8.5.3 What do we mean by safe design?437

8.5.4 Microprocessor interface circuits438

8.5.5 Mechanical contacts440

8.5.6 Conclusions440

8.6 Problems442

8.7 Appendix Ⅰ:Summary on electrical MOSFET models445

8.7.1 Naming and counting conventions445

8.7.2 The Sah model446

8.7.3 The Shichman-Hodges model450

8.7.4 The alpha-power-law model450

8.7.5 Second-order effects452

8.7.6 Effects not normally captured by transistor models455

8.7.7 Conclusions456

8.8 Appendix Ⅱ:The Bipolar Junction Transistor457

Chapter 9 Energy Efficiency and Heat Removal459

9.1 What does energy get dissipated for in CMOS circuits?459

9.1.1 Charging and discharging of capacitive loads460

9.1.2 Crossover currents465

9.1.3 Resistive loads467

9.1.4 Leakage currents468

9.1.5 Total energy dissipation470

9.1.6 CMOS voltage scaling471

9.2 How to improve energy efficiency474

9.2.1 General guidelines474

9.2.2 How to reduce dynamic dissipation476

9.2.3 How to counteract leakage482

9.3 Heat flow and heat removal488

9.4 Appendix Ⅰ:Contributions to node capacitance490

9.5 Appendix Ⅱ:Unorthodox approaches491

9.5.1 Subthreshold logic491

9.5.2 Voltage-swing-reduction techniques492

9.5.3 Adiabatic logic492

Chapter 10 Signal Integrity495

10.1 Introduction495

10.1.1 How does noise enter electronic circuits?495

10.1.2 How does noise affect digital circuits?496

10.1.3 Agenda499

10.2 Crosstalk499

10.3 Ground bounce and supply droop499

10.3.1 Coupling mechanisms due to common series impedances499

10.3.2 Where do large switching currents originate?501

10.3.3 How severe is the impact of ground bounce?501

10.4 How to mitigate ground bounce504

10.4.1 Reduce effective series impedances505

10.4.2 Separate polluters from potential victims510

10.4.3 Avoid excessive switching currents513

10.4.4 Safeguard noise margins517

10.5 Conclusions519

10.6 Problems519

10.7 Appendix:Derivation of second-order approximation521

Chapter 11 Physical Design523

11.1 Agenda523

11.2 Conducting layers and their characteristics523

11.2.1 Geometric properties and layout rules523

11.2.2 Electrical properties527

11.2.3 Connecting between layers527

11.2.4 Typical roles of conducting layers529

11.3 Cell-based back-end design531

11.3.1 Floorplanning531

11.3.2 Identify major building blocks and clock domains532

11.3.3 Establish a pin budget533

11.3.4 Find a relative arrangement of all major building blocks534

11.3.5 Plan power,clock,and signal distribution535

11.3.6 Place and route(P ＆ R)538

11.3.7 Chip assembly539

11.4 Packaging540

11.4.1 Wafer sorting543

11.4.2 Wafer testing543

11.4.3 Backgrinding and singulation544

11.4.4 Encapsulation544

11.4.5 Final testing and binning544

11.4.6 Bonding diagram and bonding rules545

11.4.7 Advanced packaging techniques546

11.4.8 Selecting a packaging technique551

11.5 Layout at the detail level551

11.5.1 Objectives of manual layout design552

11.5.2 Layout design is no WYSIWYG business552

11.5.3 Standard cell layout556

11.5.4 Sea-of-gates macro layout559

11.5.5 SRAM cell layout559

11.5.6 Lithography-friendly layouts help improve fabrication yield561

11.5.7 The mesh,a highly efficient and popular layout arrangement562

11.6 Preventing electrical overstress562

11.6.1 Electromigration562

11.6.2 Electrostatic discharge565

11.6.3 Latch-up571

11.7 Problems575

11.8 Appendix Ⅰ:Geometric quantities advertized in VLSI576

11.9 Appendix Ⅱ:On coding diffusion areas in layout drawings577

11.10 Appendix Ⅲ:Sheet resistance579

Chapter 12 Design Verification581

12.1 Uncovering timing problems581

12.1.1 What does simulation tell us about timing problems?581

12.1.2 How does timing verification help?585

12.2 How accurate are timing data?587

12.2.1 Cell delays588

12.2.2 Interconnect delays and layout parasitics593

12.2.3 Making realistic assumptions is the point597

12.3 More static verification techniques598

12.3.1 Electrical rule check598

12.3.2 Code inspection599

12.4 Post-layout design verification601

12.4.1 Design rule check602

12.4.2 Manufacturability analysis604

12.4.3 Layout extraction605

12.4.4 Layout versus schematic605

12.4.5 Equivalence checking606

12.4.6 Post-layout timing verification606

12.4.7 Power grid analysis607

12.4.8 Signal integrity analysis607

12.4.9 Post-layout simulations607

12.4.10 The overall picture607

12.5 Conclusions608

12.6 Problems609

12.7 Appendix Ⅰ:Cell and library characterization611

12.8 Appendix Ⅱ:Equivalent circuits for interconnect modelling612

Chapter 13 VLSI Economics and Project Management615

13.1 Agenda615

13.2 Models of industrial cooperation617

13.2.1 Systems assembled from standard parts exclusively617

13.2.2 Systems built around program-controlled processors618

13.2.3 Systems designed on the basis of field-programmable logic619

13.2.4 Systems designed on the basis of semi-custom ASICs620

13.2.5 Systems designed on the basis of full-custom ASICs622

13.3 Interfacing within the ASIC industry623

13.3.1 Handoff points for IC design data623

13.3.2 Scopes of IC manufacturing services624

13.4 Virtual components627

13.4.1 Copyright protection vs.customer information627

13.4.2 Design reuse demands better quality and more thorough verification628

13.4.3 Many existing virtual components need to be reworked629

13.4.4 Virtual components require follow-up services629

13.4.5 Indemnification provisions630

13.4.6 Deliverables of a comprehensive VC package630

13.4.7 Business models631

13.5 The costs of integrated circuits632

13.5.1 The impact of circuit size633

13.5.2 The impact of the fabrication process636

13.5.3 The impact of volume638

13.5.4 The impact of configurability639

13.5.5 Digest640

13.6 Fabrication avenues for small quantities642

13.6.1 Multi-project wafers642

13.6.2 Multi-layer reticles643

13.6.3 Electron beam lithography643

13.6.4 Laser programming643

13.6.5 Hardwired FPGAs and structured ASICs644

13.6.6 Cost trading644

13.7 The market side645

13.7.1 Ingredients of commercial success645

13.7.2 Commercialization stages and market priorities646

13.7.3 Service versus product649

13.7.4 Product grading650

13.8 Making a choice651

13.8.1 ASICs yes or no?651

13.8.2 Which implementation technique should one adopt?655

13.8.3 What if nothing is known for sure?657

13.8.4 Can system houses afford to ignore microelectronics?658

13.9 Keys to successful VLSI design660

13.9.1 Project definition and marketing660

13.9.2 Technical management661

13.9.3 Engineering662

13.9.4 Verification665

13.9.5 Myths665

13.10 Appendix:Doing business in microelectronics667

13.10.1 Checklists for evaluating business partners and design kits667

13.10.2 Virtual component providers669

13.10.3 Selected low-volume providers669

13.10.4 Cost estimation helps669

Chapter 14 A Primer on CMOS Technology671

14.1 The essence of MOS device physics671

14.1.1 Energy bands and electrical conduction671

14.1.2 Doping of semiconductor materials672

14.1.3 Junctions,contacts,and diodes674

14.1.4 MOSFETs676

14.2 Basic CMOS fabrication flow682

14.2.1 Key characteristics of CMOS technology682

14.2.2 Front-end-of-line fabrication steps685

14.2.3 Back-end-of-line fabrication steps688

14.2.4 Process monitoring689

14.2.5 Photolithography689

14.3 Variations on the theme697

14.3.1 Copper has replaced aluminum as interconnect material697

14.3.2 Low-permittivity interlevel dielectrics are replacing silicon dioxide698

14.3.3 High-permittivity gate dielectrics to replace silicon dioxide699

14.3.4 Strained silicon and SiGe technology701

14.3.5 Metal gates bound to come back702

14.3.6 Silicon-on-insulator(SOI)technology703

Chapter 15 Outlook706

15.1 Evolution paths for CMOS technology706

15.1.1 Classic device scaling706

15.1.2 The search for new device topologies709

15.1.3 Vertical integration711

15.1.4 The search for better semiconductor materials712

15.2 Is there life after CMOS?714

15.2.1 Non-CMOS data storage715

15.2.2 Non-CMOS data processing716

15.3 Technology push719

15.3.1 The so-called industry"laws"and the forces behind them719

15.3.2 Industrial roadmaps721

15.4 Market pull723

15.5 Evolution paths for design methodology724

15.5.1 The productivity problem724

15.5.2 Fresh approaches to architecture design727

15.6 Summary729

15.7 Six grand challenges730

15.8 Appendix:Non-semiconductor storage technologies for comparison731

Appendix A Elementary Digital Electronics732

A.1 Introduction732

A.1.1 Common number representation schemes732

A.1.2 Notational conventions for two-valued logic734

A.2 Theoretical background of combinational logic735

A.2.1 Truth table735

A.2.2 The n-cube736

A.2.3 Karnaugh map736

A.2.4 Program code and other formal languages736

A.2.5 Logic equations737

A.2.6 Two-level logic738

A.2.7 Multilevel logic740

A.2.8 Symmetric and monotone functions741

A.2.9 Threshold functions741

A.2.10 Complete gate sets742

A.2.11 Multi-output functions742

A.2.12 Logic minimization743

A.3 Circuit alternatives for implementing combinational logic747

A.3.1 Random logic747

A.3.2 Programmable logic array(PLA)747

A.3.3 Read-only memory(ROM)749

A.3.4 Array multiplier749

A.3.5 Digest750

A.4 Bistables and other memory circuits751

A.4.1 Flip-flops or edge-triggered bistables752

A.4.2 Latches or level-sensitive bistables755

A.4.3 Unclocked bistables756

A.4.4 Random access memories(RAMs)760

A.5 Transient behavior of logic circuits761

A.5.1 Glitches,a phenomenological perspective762

A.5.2 Function hazards,a circuit-independent mechanism763

A.5.3 Logic hazards,a circuit-dependent mechanism764

A.5.4 Digest765

A.6 Timing quantities766

A.6.1 Delay quantities apply to combinational and sequential circuits766

A.6.2 Timing conditions apply to sequential circuits only768

A.6.3 Secondary timing quantities770

A.6.4 Timing constraints address synthesis needs771

A.7 Microprocessor input/output transfer protocols771

A.8 Summary773

Appendix B Finite State Machines775

B.1 Abstract automata775

B.1.1 Mealy machine776

B.1.2 Moore machine777

B.1.3 Medvedev machine778

B.1.4 Relationships between finite state machine models779

B.1.5 Taxonomy of finite state machines782

B.1.6 State reduction783

B.2 Practical aspects and implementation issues785

B.2.1 Parasitic states and symbols785

B.2.2 Mealy-,Moore-,Medvedev-type,and combinational output bits787

B.2.3 Through paths and logic instability787

B.2.4 Switching hazards789

B.2.5 Hardware costs790

B.3 Summary793

Appendix C VLSI Designer's Checklist794

C.1 Design data sanity794

C.2 Pre-synthesis design verification794

C.3 Clocking795

C.4 Gate-level considerations796

C.5 Design for test797

C.6 Electrical considerations798

C.7 Pre-layout design verification799

C.8 Physical considerations800

C.9 Post-layout design verification800

C.10 Preparation for testing of fabricated prototypes801

C.11 Thermal considerations802

C.12 Board-level operation and testing802

C.13 Documentation802

Appendix D Symbols and constants804

D.1 Mathematical symbols used804

D.2 Abbreviations807

D.3 Physical and material constants808

References811

Index832